Firm creates world’s smallest 1G memory chip

Matrix Semiconductor today announced the world’s smallest one-gigabit silicon memory at 31 square millimeters, the development of which was based on two technology breakthroughs that extend Matrix’s leadership role in three-dimensional semiconductor design: Hybrid Scaling and the Segmented Wordline architecture. Through the use of these two innovations, Matrix was able to double Matrix® 3-D Memory’s (3DM) bit capacity, using the same area of silicon, in less than one year. Matrix will continue to double density with each new version of its 3-D memory for years to come, providing high capacities at the lowest absolute silicon cost.

Unique to a 3-D integrated circuit, Hybrid Scaling is the combination of different process geometries within the layers of a 3-D circuit. This approach takes Matrix 3DM’s leading memory densities even further than predicted by Moore’s Law.

The first use of Hybrid Scaling by Matrix features base logic layers manufactured at 150-nanometer rules and subsequent memory layers at 130-nanometer rules. This allows Matrix to shorten its development time and achieve faster time-to-market by increasing the number of memory bits possible on top of a given logic array. Furthermore, Matrix is able to attain this using existing 180-nanometer toolsets, achieving state-of-the-art results with mature, lower-cost, fabrication processes. Future products from Matrix will continue to use this manufacturing approach, at progressively more advanced design rules, to achieve the most cost-effective memories possible.

The Segmented Wordline architecture – for which Matrix received its 100th patent – minimizes the effect of non-memory logic circuitry on silicon utilization. In traditional memory designs, the amount of silicon not used in the memory array lowers the overall manufacturing efficiency of the memory chip. Matrix’s three-dimensional approach alleviates this problem by building the memory array on top of the logic circuitry. The Segmented Wordline architecture results in a far more efficient use of silicon, reducing the die’s area by nearly 25%.

“Matrix is the industry’s leading innovator in the creation of three-dimensional integrated circuits,” said Dennis Segers, president and CEO of Matrix Semiconductor. “The development of Hybrid Scaling and the Segmented Wordline architecture form the foundation for this new family of products and enable Matrix’s roadmap to scale 3-D technology for years to come.”

The combination of Hybrid Scaling and the Segmented Wordline architecture presents an accelerated, economical, and sustainable scalability advantage, which Matrix will continue to apply to future versions of Matrix 3DM. In maintaining a strategy of using mature manufacturing processes, Matrix ensures it will continue to scale 3DM to progressively higher levels of integration which will exceed those of memory products made using state-of-the-art planar techniques.

By the end of 2005, Matrix will have applied these technologies across all of the memory capacities it currently offers (128-, 256-, and 512-megabit) as well as the new one-gigabit 3-D memory. Samples of these new products are available this quarter, and will be shipping in volume to customers in Q3 of 2005.

Matrix is the only company that builds integrated circuits in three dimensions producing cost-effective IC memory products by combining the supporting logic layers with multiple layers of memory on a single piece of silicon, making the most efficient use of a silicon wafer. Matrix 3DM is a permanent, programmable, non-volatile memory and the first product line developed by Matrix to be based on this technology. By using proven manufacturing techniques with the third dimension, Matrix derives lower cost and more components per wafer than any other comparable memory product on today’s market.

About Matrix Semiconductor
Matrix Semiconductor, Inc. is the creator and developer of the world’s first three-dimensional integrated circuits. Matrix’s first product, Matrix® 3-D Memory (3DM), is a low cost, high density line of permanent, programmable, non-volatile memory that is compatible with existing standards. Matrix 3-D Memory accelerates time-to-market for publishers of digital content and is targeted for use in portable consumer electronic devices.

Privately held, Matrix is headquartered in Santa Clara, California. Additional information may be found at: http://www.matrixsemi.com

From Matrix Semiconductor

The material in this press release comes from the originating research organization. Content may be edited for style and length. Want more? Sign up for our daily email.